r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1833

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
23 to 16
15
14 to 12
11
10 to 8
Bit Name
AIV
DBE
SZ
ETBE
—
Initial
Value
All 0
0
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
ASID Specify
Specifies the ASID value to be included in the match
conditions.
Data Value Enable*
Specifies whether or not to include the data value in the
match condition. This bit is valid only when the operand
access cycle is specified as a match condition.
0: The data value is not included in the match
1: The data value is included in the match conditions.
Operand Size Select
Specifies the operand size to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
000: The operand size is not included in the match
001: Byte access
010: Word access
011: Longword access
100: Quadword access*
Others: Reserved (setting prohibited)
Execution Count Value Enable
Specifies whether or not to include the execution count
value in the match conditions. If this bit is 1 and the
match condition satisfaction count matches the value
specified by the CETR1 register, the operation specified
by the CRR1 register is performed.
0: The execution count value is not included in the
1: The execution count value is included in the match
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
conditions; thus, not checked.
match conditions; thus, not checked.
conditions.
condition; thus, not checked (any operand size
specifies the match condition). *
Rev. 1.00 Oct. 01, 2007 Page 1767 of 1956
Section 41 User Break Controller (UBC)
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2
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REJ09B0256-0100