r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1102

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 26 I
26.3.5
Rev. 1.00 Oct. 01, 2007 Page 1036 of 1956
REJ09B0256-0100
Bit
7
6
5
Master Control Register (ICMCR)
2
C Bus Interface (IIC)
Bit Name
MDBS
FSCL
FSDA
Initial value:
R/W:
Initial Value
0
—
—
BIt:
MDBS
R
7
0
FSCL
R/W
6
−
R/W
R/W
R/W
R/W
FSDA
R/W
−
5
OBPC
R/W
4
0
Description
Master Data Buffer Select
This bit is used to select the data buffer. The
double-buffer mode and singe-buffer mode are
available.
When this bit is set to 0, the double-buffer
mode is selected. During a reception, as long
as both buffers are full and the MDR flag has
not been cleared, SCL is held low. When the
MDR flag is cleared, the low level state of SCL
is released.
When this bit is set to 1, the single-buffer mode
is selected. SCL will be held low from the
timing when the receive data register acquires
the data packet until the MDR flag is cleared.
0: Double-buffer mode
1: Single-buffer mode
Forced SCL
This bit controls the status of the I2C_SCL pin
(reading reflects the current level on the I
bus). When the OBPC bit is set, this bit directly
controls the SCL line on the bus.
During a read cycle, the level on this bit (which
includes the reset level) will change depending
on the level on I2C_SCL since it reflects the
level on the I2C_SCL.
Forced SDA
This bit controls the status of the I2C_SDA pin
(reading reflects the busy status level on the
I2C_SDA). When the OBPC bit is set then this
bit directly controls the SDA line on the bus.
During a read cycle, the level of this bit (which
includes the reset level) will show the busy
status of the I
busy).
R/W
MIE
3
0
TSBE
R/W
2
0
2
C bus (1 for busy; 0 for not
R/W
FSB
1
0
R/W
ESG
0
0
2
C