r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1268

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
29.3.7
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR
can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't care.).
Rev. 1.00 Oct. 01, 2007 Page 1202 of 1956
REJ09B0256-0100
Initial value:
Initial value:
Bit
31 to 16 SIRC0[15:0]
15 to 0
R/W:
R/W:
BIt:
BIt:
Receive Control Data Register (SIRCR)
Bit Name
SIRC1[15:0]
R/W
R/W
31
15
—
—
R/W
R/W
30
14
—
—
R/W
R/W
29
13
—
—
Initial
Value
Undefined
Undefined
R/W
R/W
28
12
—
—
R/W
R/W
27
—
11
—
R/W
R/W
R/W
R/W
R/W
26
10
—
—
Control Channel 0 Receive Data
Control Channel 1 Receive Data
Description
Store data received from the SIOF_RXD pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmit or receive frame is
specified by the CD0A bit in SICDAR.
•
Store data received from the SIOF_RXD pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmit or receive frame is
specified by the CD1A bit in SICDAR.
•
R/W
R/W
25
—
—
9
These bits are valid only when the CD0E bit in
SICDAR is set to 1.
These bits are valid only when the CD1E bit in
SICDAR is set to 1.
SIRC0[15:0]
SIRC1[15:0]
R/W
R/W
24
—
—
8
R/W
R/W
23
—
—
7
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
R/W
R/W
18
—
—
2
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0