r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 648

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 14 Direct Memory Access Controller (DMAC)
Rev. 1.00 Oct. 01, 2007 Page 582 of 1956
REJ09B0256-0100
Bit
7
6
5
4, 3
2
Bit Name
DL
DS
TB
TS[1:0]
IE
Initial
Value
0
0
0
00
0
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
DREQ Level and DREQ Edge Select
Specify the detecting method of the DREQ pin input
and the detecting level.
These bits are valid only in CHCR0 to CHCR3.
In channels 0 to 3, also, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, these bits are invalid.
00: DREQ detected at low level
01: DREQ detected at falling edge
10: DREQ detected at high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
Burst mode cannot be used when the on-chip
peripheral module is the transfer request source.
DMA Transfer Size Specify
See the description of TS[2] (bit 20).
Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request (DEI)
to the CPU when the TE bit is set to 1.
0: Interrupt request is disabled.
1: Interrupt request is enabled.