r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 699
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 699 of 2026
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The CPG generates clocks provided to the on-chip peripheral modules and external bus interface
of this LSI, and controls the power-down mode function. The CPG consists of an oscillator, PLL
circuits, frequency dividers, and control circuits.
16.1
• Clocks used for LSI internal operation
• Clocks supplied to outside modules
• Clock modes
• Power-down mode control
Generates the CPU clock (Ick) used by the CPU, FPU, cache, and TLB, SHwy clock (SHck)
used by the SuperHyway, and peripheral clocks (Pck0, Pck1) supplied to the peripheral
modules.
Generates the bus clock (Bck) used by the external bus interface and the memory clocks
(DDRck) used by the DDR interface.
Either a crystal resonator or an externally input clock can be selected as the CPG clock input.
The combination of the division ratios for the CPU clock, SHwy clock, bus clock, peripheral
clock, and DDR-memory clock after a power-on reset can be selected from two clock
operating modes.
The clock can be stopped for sleep mode and software standby mode, and specific modules can
be stopped in module standby mode.
Features
Section 16 Clock Pulse Generator (CPG)
Rev. 1.00 Oct. 01, 2007 Page 633 of 1956
Section 16 Clock Pulse Generator (CPG)
REJ09B0256-0100
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