r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 885

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.7
MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. Return the E-MAC and E-DMAC to their initial states by means of the SWRT and
SWRR bits in EDMR before making settings again.
Bit
31 to 16
15 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
MAC Address Low Register (MALR)
Bit Name

MA[15:0]
R/W
31
15

R
0
0
R/W
30
14

R
0
0
R/W
29
13

R
0
0
Initial
Value
All 0
All 0
R/W
28
12

R
0
0
R/W
27
11
R/W
R
R/W

R
0
0
R/W
26
10

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
MAC Address Bits 15 to 0
These bits are used to set the lower 16 bits of the MAC
address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), set H'000089AB in this register.
R/W
25

R
0
9
0
R/W
24

R
0
8
0
MA[15:0]
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
23

R
0
7
0
R/W
Rev. 1.00 Oct. 01, 2007 Page 819 of 1956
22

R
0
6
0
R/W
21

R
0
5
0
R/W
20

R
0
4
0
R/W
19

R
0
3
0
REJ09B0256-0100
R/W
18

R
0
2
0
17

R
0
1
0
R/W
16

R
0
0
0