r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1290

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
Table 29.9 Audio Mode Specification for Receive Data
Note: Left and right same audio mode is not supported in receive data.
(2)
Control data is written to or read from by the following registers.
• Transmit control data write: SITCR (32-bit access)
• Receive control data read: SIRCR (32-bit access)
Figure 29.6 shows the control data and bit alignment in SITCR and SIRCR.
The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR.
Table 29.10 shows the relationship between the number of channels in control data and bit
settings.
Rev. 1.00 Oct. 01, 2007 Page 1224 of 1956
REJ09B0256-0100
Mode
Monaural
Stereo
Control Data
To execute 8-bit monaural transmission or reception, use the left channel.
(a) Control data: One channel
(b) Control data: Two channels
31
31
Figure 29.6 Control Data Bit Alignment
Control data
Control data
(channel 0)
(channel 0)
24 23
24 23
RDLE
1
1
16 15
16 15
Control data
(channel 1)
8 7
8 7
Bit
RDRE
0
1
0
0