r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 473

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
11.5.10 Master Mode
The master mode processor holds the bus itself unless it receives a bus request.
On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master
mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as
soon as the currently executing bus cycle ends. On receiving the BREQ negation (high level)
indicating that the slave has released the bus, the processor negates (drives high) the BACK signal
and resumes use of the bus.
When the bus is released, all bus interface related output signals and input/output signals go to the
high-impedance state, except for the synchronous DRAM interface M_CKE signal and bus
arbitration BACK signal, DACK0 to DACK3, and TEND0 to TEND3 which control DMA
transfers.
The actual bus release sequence is as follows.
First, the bus use permission signal is asserted in synchronization with the rising edge of the clock.
The address bus and data bus go to the high-impedance state in synchronization from next rising
edge of the clock after this BACK assertion. At the same time, the bus control signals (BS, CSn,
WEn, RD, RDWR, CE2A, and CE2B) go to the high-impedance state. These bus control signals
are negated no later than one cycle before going to high-impedance. Bus request signal sampling
is performed on the rising edge of the clock.
The sequence for re-acquiring the bus from the slave is as follows.
As soon as BREQ negation is detected on the rising edge of the clock, BACK is negated and bus
control signal driving is started. Driving of the address bus and data bus starts at the next rising
edge of an in-phase clock. The bus control signals are asserted and the bus cycle is actually
started, at the earliest, at the clock rising edge at which the address and data signals are driven.
In order to reacquire the bus and start execution of bus access, the BREQ signal must be negated
for at least two cycles.
Rev. 1.00 Oct. 01, 2007 Page 407 of 1956
REJ09B0256-0100