r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1292

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
(1)
Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot
position of control data. This method can be used in both SIOF master and slave modes. Figure
29.7 shows an example of the control data interface timing by slot position control.
(2)
The CODEC normally outputs the SIOF_SYNC signal as synchronization pulse (FS). In this
method, the CODEC outputs the secondary FS specific to the control data transfer after 1/2 frame
time has been passed (not the normal FS output timing) to transmit or receive control data. This
method is valid for SIOF slave mode. The following summarizes the control data interface
procedure by the secondary FS.
• Transmit normal transmit data of LSB = 0 (the SIOF forcibly clears 0).
• To execute control data transmission, send transmit data of LSB = 1 (the SIOF forcibly set to 1
• The CODEC outputs the secondary FS.
• The SIOF transmits or receives (stores in SIRCR) control data (data specified by SITCR)
Rev. 1.00 Oct. 01, 2007 Page 1226 of 1956
REJ09B0256-0100
SIOF_RXD
SIOF_SCK
SIOF_SYNC
SIOF_TXD
by writing SITCR).
synchronously with the secondary FS.
Control by Slot Position (Master Mode 1, Slave Mode 1)
Control by Secondary FS (Slave Mode 2)
Specifications: TRMD[1:0] = 00 or 10,
Slot No.0
L-channel
data
Figure 29.7 Control Data Interface (Slot Position)
TDLE = 1,
RDLE = 1,
CD0E = 1,
channel 0
Slot No.1
Control
R-channel
Slot No.2
data
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0001,
channel 1
Slot No.3
Control
1 frame
FL[3:0] = 1110 (Frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
TDRA[3:0] = 0010,
RDRA[3:0] = 0010,
CD1A[3:0] = 0011