r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1113

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

26.4.6
Figure 26.3 shows the format of data transfer from a master to a slave device (master data transmit
format). Figure 26.4 shows the data transfer format (master data receive format) when a master
device reads the second and the following byte data from a slave device.
Figure 26.5 shows the combined format when the data transfer direction changes during one
transfer. When changing the direction after the first transfer, the repeated START condition (Sr),
slave address and R/W bits are transmitted. In this case, the R/W bit is set to the direction opposite
to the first transfer direction. The repeated START condition is issued by the master at the end of a
transmit or receive cycle if the enable start generation bit in the master control register has been
set.
7-Bit Address Format
S
S
:
:
From MASTER to SLAVE
From SLAVE to MASTER
SLAVE ADDRESS
SLAVE ADDRESS
Figure 26.3 Master Data Transmit Format
Figure 26.4 Master Data Receive Format
0(Write)
1(Read)
R/W
R/W
A
A
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
S = Strat condition
P = Stop condition
DATA
DATA
(n Bytes + ACKNOWLEDGE)
(n Bytes + ACKNOWLEDGE)
Data transferres
Data transferred
Rev. 1.00 Oct. 01, 2007 Page 1047 of 1956
A
A
DATA
DATA
Section 26 I
A/A
A/A
2
C Bus Interface (IIC)
REJ09B0256-0100
P
P