r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 301

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.1.1
The basic exception handling flow for the interrupt is as follows.
In interrupt exception handling, the contents of the program counter (PC), status register (SR), and
R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general
register15 (SGR), and the CPU starts execution of the appropriate interrupt exception handling
routine according to the vector address. An interrupt exception handling routine is a program
written by the user to handle a specific exception. The interrupt exception handling routine is
terminated and control returned to the original program by executing a return-from-exception
instruction (RTE). This instruction restores the PC and SR contents and returns control to the
normal processing routine at the point at which the exception occurred. The SGR contents are not
written back to R15 with an RTE instruction.
1. The PC, SR and R15 contents are saved to SPC, SSR and SGR, respectively.
2. The block (BL) bit in SR is set to 1.
3. The mode (MD) bit in SR is set to 1.
4. The register bank (RB) bit in SR is set to 1.
5. In a reset, the FPU disable (FD) bit in SR is cleared to 0.
6. The exception code is written to bits 13 to 0 in the interrupt event register (INTEVT) of the
7. The processing is jumped to the start address of the interrupt exception handling routine,
8. The processing is branched to the vector address of the determined interrupt exception
exception source.
vector base register (VBR) + H'600.
handling and the interrupt exception handling routine is started.
Interrupt Method
Rev. 1.00 Oct. 01, 2007 Page 235 of 1956
Section 9 Interrupt Controller (INTC)
REJ09B0256-0100