r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 182

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 5 Exception Handling
5.6
The various exception handling operations explained here are exception sources, transition address
on the occurrence of exception, and processor operation when a transition is made.
5.6.1
(1)
• Condition:
• Operations:
(2)
• Condition:
• Operations:
(3)
• Source: SDIR.TI[7:4] = B'0110 (negation) or B'0111 (assertion)
• Transition address: H'A0000000
• Transition operations:
Rev. 1.00 Oct. 01, 2007 Page 116 of 1956
REJ09B0256-0100
Power-on reset request
Exception code H'000 is set in EXPEVT, initialization of the CPU and on-chip peripheral
module is carried out, and then a branch is made to the reset vector (H'A0000000). For details,
see the register descriptions in the relevant sections. A power-on reset should be executed
when power is supplied.
Manual reset request
Exception code H'020 is set in EXPEVT, initialization of the CPU and on-chip peripheral
module is carried out, and then a branch is made to the branch vector (H'A0000000). The
registers initialized by a power-on reset and manual reset are different. For details, see the
register descriptions in the relevant sections.
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
Power-On Reset
Manual Reset
H-UDI Reset
Description of Exceptions
Resets

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