r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 111

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

2.2.4
(1)
Bit
31
30
29
28
Initial value:
Initial value:
Status Register (SR)
R/W:
R/W:
BIt:
BIt:
Control Registers
Bit Name
—
MD
RB
BL
R/W
FD
31
15
R
0
0
R/W
MD
30
14
R
1
0
R/W
RB
29
13
R
Initial
Value
0
1
1
1
1
0
R/W
28
BL
12
R
1
0
R/W
R
R/W
R/W
R/W
27
11
R
R
0
0
26
10
R
R
0
0
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Processing Mode
Selects the processing mode.
0: User mode (Some instructions cannot be executed
This bit is set to 1 by an exception or interrupt.
Privileged Mode General Register Bank Specification
Bit
0: R0_BANK0 to R7_BANK0 are accessed as general
1: R0_BANK1 to R7_BANK1 are accessed as general
This bit is set to 1 by an exception or interrupt.
Exception/Interrupt Block Bit
This bit is set to 1 by a reset, an exception, or an
interrupt. While this bit is set to 1, an interrupt request
is masked. In this case, this processor enters the reset
state when a general exception other than a user
break occurs.
R/W
25
M
R
0
9
0
registers R0 to R7 and R0_BANK1 to R7_BANK1
can be accessed using LDC/STC instructions
registers R0 to R7 and R0_BANK0–R7_BANK0
can be accessed using LDC/STC instructions
and some resources cannot be accessed.)
1: Privileged mode
R/W
24
Q
R
0
8
0
R/W
23
R
0
7
1
R/W
22
R
0
6
1
Rev. 1.00 Oct. 01, 2007 Page 45 of 1956
IMASK
R/W
21
R
5
0
1
Section 2 Programming Model
R/W
20
R
0
4
1
19
R
R
0
3
0
REJ09B0256-0100
18
R
R
0
2
0
R/W
17
R
S
0
1
0
R/W
16
R
T
0
0
0