r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 385

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

The local bus state controller (LBSC) divides the external memory space and outputs control

signals corresponding to the specifications of various types of memory and bus interfaces. The

LBSC enables the connection of SRAM or ROM, etc., to this LSI. It also supports the PCMCIA

interface protocol, which is used to implement simplified system design and high-speed data

transfers in a compact system.

The LBSC has the following features.

• Controls six areas, areas 0 to 2 and 4 to 6, of an external memory space divided into seven

• SRAM interface

• Burst ROM interface

 Maximum 64 Mbytes for each of areas 0 to 2 and 4 to 6

 Bus width of each area can be controlled through register settings (except area 0, which is

 Wait-cycle insertion by the RDY pin

 Wait-cycle insertion can be controlled by a program

 Types of memory are specifiable for connection to each area

 Output of the control signals of memory to each area

 Automatic wait cycle insertion to prevent data bus collisions on consecutive memory

 Insertion of cycles to ensure the setup time and hold time to the write strobe on a write

 Wait-cycle insertion can be controlled by a program

 Insertion of the wait cycle through the RDY pin

 Wait-cycle insertion can be controlled by a program

 Burst length specified by the register

controlled by the external pin setting)

accesses to different areas, or a read access followed by a write access to the same area

cycle enables connection to low-speed memory

Connectable areas : 0 to 2 and 4 to 6

Settable bus widths: 32, 16, and 8 bits

Connectable areas: 0 to 2 and 4 to 6

Settable bus widths: 32, 16, and 8 bits

Section 11 Local Bus State Controller (LBSC)

Rev. 1.00 Oct. 01, 2007 Page 319 of 1956

REJ09B0256-0100