r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 972

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.70 E-DMAC Transmit Request Register (EDTRR)
EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After
writing 11 to bits TR[1:0] in this register, the E-DMAC reads the transmit descriptor at the address
specified by TDLAR. If the TACT bit of this transmit descriptor is set to 1 (valid), transmit DMA
transfer by the E-DMAC starts. When DMA transfer based on the first transmit descriptor is
completed, the E-DMAC reads the next transmit descriptor. If the TACT bit of that transmit
descriptor is set to 1 (valid), the E-DMAC continues transmit DMA operation. If the TACT bit of
a transmit descriptor is cleared to 0 (invalid), the E-DMAC clears bits TR[1:0] and stops transmit
DMA operation.
Rev. 1.00 Oct. 01, 2007 Page 906 of 1956
REJ09B0256-0100
Bit
31 to 2
1, 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

TR[1:0]
31
15


R
R
0
0
30
14


R
R
0
0
Initial
Value
All 0
00
29
13


R
R
0
0
28
12


R
R
0
0
R/W Description
R
R/W Transmit Request
27
11


R
R
0
0
Reserved
These bits are always read as 0. The write value should
always be 0.
00, 01, 10: Transmission-halted state
11: Transmit DMA operation by E-DMAC
26
10

R

R
0
0
After writing 11 to these bits, the E-DMAC starts
reading a transmit descriptor.
25


R
R
0
9
0
24
If 00, 01, or 10 is written to these bits, the E-
DMAC stops DMA transfer of the currently
processed transmit descriptor, reads the next
transmit descriptor, and then clears these bits.
(Write-back is completed for the valid transmit
descriptors that have been detected up till then.)
The E-DMAC clears these bits when transmit
descriptor empty occurs, or transmission of a
transmit descriptor has completed. (Write-back
is completed for the valid transmit descriptors
that have been detected up till then.)


R
R
0
8
0
23


R
R
0
7
0
22


R
R
0
6
0
21

R

R
0
5
0
20

R

R
0
4
0
19


R
R
0
3
0
18


R
R
0
2
0
17

R
0
1
0
TR[1:0]
R/W
16

R
0
0
0