r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 986

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)

23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER)

TRSCER specifies whether the information for the transmit and receive state reported by bits 17,

16, and 10 to 0 in the E-MAC/E-DMAC status register (EESR) is to be reflected in the TFE or

RFE bit of the corresponding descriptor. The bits in this register correspond to bits 17, 16, and 10

to 0 in EESR. When a bit is cleared to 0, the transmit status (bits 17 and 10 to 8 in EESR) is

reflected in the TFE bit of the transmit descriptor, and the receive status (bits 16 and 7 to 0 in

EESR) is reflected in the RFE bit of the receive descriptor. In this case, the state of a status bit set

to 1 is reflected as the TFE or RFE bit set to 1. When a bit is set to 1, the occurrence of the

corresponding source is not reflected in the descriptor. After this LSI is reset, all bits are cleared to

Rev. 1.00 Oct. 01, 2007 Page 920 of 1956

REJ09B0256-0100

Initial value:

These bits are always read as 0. The write value should

always be 0.

TABT Bit Copy Directive

0: Reflects the TABT bit status in the TFE bit of the

1: Occurrence of the corresponding source is not

RABT Bit Copy Directive

0: Reflects the RABT bit status in the RFE bit of the

1: Occurrence of the corresponding source is not

transmit descriptor

reflected in the TFE bit of the transmit descriptor

receive descriptor

reflected in the RFE bit of the receive descriptor