r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 504

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 12 DDR-SDRAM Interface (DDRIF)

Figures 12.5 to 12.14 show examples of basic DDRIF timing.

In every figure, the DDR-SDRAM is idle at T0.

The various timings should be set in the STR register within the range specified by the DDR-

Note that the DDRIF only supports 2.5-cycle CAS latency (CL).

Rev. 1.00 Oct. 01, 2007 Page 438 of 1956

REJ09B0256-0100

Figure 12.5 Basic DDRIF Timing (1 Burst Read: 1, 2, 4, or 8 Bytes; Without Auto-

DDRIF Basic Timing