r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 171

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

5.1
Exception handling processing is handled by a special routine which is executed by a reset,
general exception handling, or interrupt. For example, if the executing instruction ends
abnormally, appropriate action must be taken in order to return to the original program sequence,
or report the abnormality before terminating the processing. The process of generating an
exception handling request in response to abnormal termination, and passing control to a user-
written exception handling routine, in order to support such functions, is given the generic name of
exception handling.
The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts.
5.2
Table 5.1 lists the configuration of registers related exception handling.
Table 5.1
Note:
Table 5.2
Register Name
TRAPA exception register
Exception event register
Interrupt event register
Register Name
TRAPA exception register
Exception event register
Interrupt event register
*
Summary of Exception Handling
Register Descriptions
P4 is the address when virtual address space P4 area is used. Area 7 is the address
when physical address space area 7 is accessed by using the TLB.
Register Configuration
States of Register in Each Operating Mode
Section 5 Exception Handling
Abbr.
TRA
EXPEVT
INTEVT
Abbr.
TRA
EXPEVT
INTEVT
H'0000 0000 H'0000 0020
R/W
R/W
R/W
R/W
Power-on
Reset
Undefined
Undefined
P4 Address*
H'FF00 0020
H'FF00 0024
H'FF00 0028
Manual Reset Sleep
Undefined
Undefined
Rev. 1.00 Oct. 01, 2007 Page 105 of 1956
Area 7
Address*
H'1F00 0020
H'1F00 0024
H'1F00 0028
Retained
Retained
Retained
Section 5 Exception Handling
Standby
Retained
Retained
Retained
REJ09B0256-0100
Access Size
32
32
32