r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 269

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

7.4.2
When the IC is enabled (ICE = 1 in CCR) and instruction prefetches are performed from a
cacheable area, the instruction cache operates as follows:
1. The tag, V bit, Ubit and LRU bits on each way are read from the cache line indexed by virtual
2. The tag, read from each way, is compared with bits [28:10] of the physical address resulting
• If there is a way whose tag matches and the V bit is 1, see No. 3.
• If there is no way whose tag matches and the V bit is 1, see No. 4.
3. Cache hit
4. Cache miss
7.4.3
When the IC2W bit in RAMCR is set to 1, IC two-way mode which only uses way 0 and way 1 in
the IC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1
are used even if a memory-mapped IC access is made.
The IC2W bit should be modified by a program in the P2 area. At that time, if the valid line has
already been recorded in the IC, 1 should be written to the ICI bit in CCR and all entries in the IC
should be invalid before modifying the IC2W bit.
address bits [12:5].
from virtual address translation by the MMU:
The LRU bits is updated to indicate the way is the latest one.
Data is read into the cache line on a way which selected using the LRU bits to replace from the
physical address space corresponding to the virtual address. Data reading is performed, using
the wraparound method, in order from the quad-word data (8 bytes) including the cache-
missed data. In the prefetch opreration, the CPU doesn't wait the data arrived. While the one
cache line of data is being read, the CPU can execute the next processing. When reading of one
line of data is completed, the tag corresponding to the physical address is recorded in the
cache, and 1 is written to the V bit, the LRU bits is updated to indicate the way is the latest
one.
Prefetch Operation
IC Two-Way Mode
Rev. 1.00 Oct. 01, 2007 Page 203 of 1956
Section 7 Caches
REJ09B0256-0100