r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 977

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Frame Transmission Complete

Indicates, in combination with the TC[0] bit, that all the

data specified by the transmit descriptor has been

transmitted from the E-MAC. This bit is set to 1 on

assuming the completion of transmission. This is when

transmission of one frame is completed and the

transmit descriptor valid bit (TACT) of the next transmit

descriptor not being set in single-frame/single-

descriptor operation or when the last data of a frame

has been transmitted and the transmit descriptor valid

bit (TACT) of the next descriptor not being set in multi-

buffer frame processing based on single-frame/multi-

descriptor operation. After frame transmission has

completed, the E-DMAC writes the transmission status

back to the relevant descriptor.

00: Transmission has not completed, or no

11: Transmission has completed

Others: Setting disabled

Transmit Underflow Frame Write-Back Complete

0: Write-back has not completed for the frame causing

1: Write-back has completed for the frame causing

Receive Overflow Frame Write-Back Complete

0: Write-back has not completed for the frame causing

1: Write-back has completed for the frame causing

Transmit Abort Detect

Indicates that the E-MAC aborts transmitting a frame

because of failures during frame transmission.

0: Frame transmission has not been aborted or no

1: Frame transmission has been aborted

transmit underflow

receive overflow

transmission directive

Section 23 Gigabit Ethernet Controller (GETHER)

Rev. 1.00 Oct. 01, 2007 Page 911 of 1956

REJ09B0256-0100