r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1319

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Bit
6
Bit Name
RDRF
Initial
Value
0
R/W
R/W
Receive Data Register Full
Description
Indicates that received data is stored in the receive data
register (SCRDR).
0: Indicates that no valid received data is stored in SCRDR
[Clearing conditions]
1: Indicates that valid received data is stored in SCRDR
[Setting condition]
When serial reception is completed normally, and received
data is transferred from SCRSR to SCRDR.
Note: In T = 0 mode, when a parity error is detected during
On reset
When data is read from SCRDR
When 0 is written to RDRF
reception, the SCRDR contents and RDRF flag are
unaffected, and the previous state is retained.
On the other hand, in T = 1 mode, when a parity
error is detected during reception, the received data
is transferred to SCRDR, and the RDRF flag is set
to 1.
In both T = 0 and T = 1 modes, even if the RE bit in
the serial control register (SCSCR) is cleared to 0,
the SCRDR contents and RDRF flag are unaffected,
and the previous state is retained.
Rev. 1.00 Oct. 01, 2007 Page 1253 of 1956
Section 30 SIM Card Module (SIM)
REJ09B0256-0100

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