r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1072

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 25 Stream Interface (STIF)
25.3.2
STICR enables or disables the STIF module and sets the packet interval for stream data
transmission.
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 1006 of 1956
REJ09B0256-0100
Bit
31 to 28 
27 to 16 ICYC[11:0] All 0
15
14 to 1
0
R/W:
R/W:
Bit:
Bit:
Control Registers 0, 1 (STICR0, STICR1)
Bit Name

EN
RST
RTS
R/W
−
31
15
R
0
0
30
−
14
−
R
R
0
0
Initial
Value
All 0
0
All 0
0
−
−
29
13
R
R
0
0
−
−
28
12
R
R
0
0
R/W
27
11
−
R
0
0
R/W
R
R/W
R/W
R
R/W
R/W
26
10
−
R
0
0
Description
These bits are always read as 0. The write value
should always be 0.
Number of Cycles between Transmit Packets
These bits set the fixed value when a fixed value is
used as the number of cycles between packets
during transmission. 1 to 4096 cycles of peripheral
clock 0 can be inserted as idle cycles between
packets.
Writing 1 to this bit resets the STIF module. This bit is
always read as 0.
These bits are always read as 0. The write value
should always be 0.
STIF Module Enable
0: STIF module is disabled
1: STIF module is enabled
Reserved
STIF Module Reset
Reserved
R/W
25
−
R
0
9
0
R/W
24
R
0
8
−
0
R/W
23
−
R
0
7
0
ICYC[11:0]
R/W
22
−
R
0
6
0
R/W
21
−
R
0
5
0
R/W
20
−
R
0
4
0
R/W
19
−
R
0
3
0
R/W
18
−
R
0
2
0
R/W
17
−
0
1
0
R/W
R/W
EN
16
0
0
0