r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 16

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

13.5 Usage Notes ....................................................................................................................... 562
Section 14 Direct Memory Access Controller (DMAC)................................... 565
14.1 Features.............................................................................................................................. 565
14.2 Input/Output Pins............................................................................................................... 567
14.3 Register Descriptions......................................................................................................... 569
14.4 Operation ........................................................................................................................... 591
14.5 Usage Notes ....................................................................................................................... 614
Rev. 1.00 Oct. 01, 2007 Page xvi of lxvi
13.4.6 Normal mode ........................................................................................................ 549
13.4.7 Power Management .............................................................................................. 549
13.4.8 PCI Local Bus Basic Interface.............................................................................. 550
13.5.1 Notes on PCIC Target Reading............................................................................. 562
13.5.2 Notes on Host Mode ............................................................................................. 562
14.3.1 DMA Source Address Registers (SAR0 to SAR5) ............................................... 572
14.3.2 DMA Source Address Registers (SARB0 to SARB3).......................................... 573
14.3.3 DMA Destination Address Registers (DAR0 to DAR5) ...................................... 573
14.3.4 DMA Destination Address Registers (DARB0 to DARB3) ................................. 574
14.3.5 DMA Transfer Count Registers (TCR0 to TCR5)................................................ 574
14.3.6 DMA Transfer Count Registers (TCRB0 to TCRB3)........................................... 575
14.3.7 DMA Channel Control Registers (CHCR0 to CHCR5) ....................................... 576
14.3.8 DMA Operation Register (DMAOR) ................................................................... 584
14.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)............................. 587
14.4.1 DMA Transfer Requests ....................................................................................... 591
14.4.2 Channel Priority.................................................................................................... 595
14.4.3 DMA Transfer Types............................................................................................ 598
14.4.4 DMA Transfer Flow ............................................................................................. 606
14.4.5 Repeat Mode Transfer .......................................................................................... 608
14.4.6 Reload Mode Transfer .......................................................................................... 609
14.4.7 DREQ Pin Sampling Timing ................................................................................ 610
14.5.1 Module Stop ......................................................................................................... 614
14.5.2 Address Error........................................................................................................ 614
14.5.3 Notes on Burst Mode Transfer.............................................................................. 614
14.5.4 DACK and TEND Output Divisions .................................................................... 615
14.5.5 CS Output Settings and Transfer Size Larger than External Bus Width............... 615
14.5.6 DACK and TEND Assertion and DREQ Sampling.............................................. 615
14.5.7 DMA Transfer to DMAC Prohibited.................................................................... 619
14.5.8 NMI Interrupt........................................................................................................ 619