r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 228

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Memory Management Unit (MMU)
6.4
6.4.1
This LSI supports the following MMU functions.
1. The MMU decodes the virtual address to be accessed by software, and performs address
2. The MMU determines the cache access status on the basis of the page management
3. If address translation cannot be performed normally in a data access or instruction access, the
4. If address translation information is not recorded in the ITLB in an instruction access, the
6.4.2
Software processing for the MMU consists of the following:
1. Setting of MMU-related registers. Some registers are also partially updated by hardware
2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB
3. MMU exception handling. When an MMU exception occurs, processing is performed based on
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REJ09B0256-0100
translation by controlling the UTLB/ITLB in accordance with the MMUCR settings.
information read during address translation (C and WT bits).
MMU notifies software by means of an MMU exception.
MMU searches the UTLB. If the necessary address translation information is recorded in the
UTLB, the MMU copies this information into the ITLB in accordance with the LRUI bit
setting in MMUCR.
automatically.
entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB.
ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. Deleting
or reading UTLB/ITLB entries is enabled by accessing the memory-mapped UTLB/ITLB.
information set by hardware.
MMU Functions
MMU Hardware Management
MMU Software Management