r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 478

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 DDR-SDRAM Interface (DDRIF)
12.3
12.3.1
Data Alignment in DDR-SDRAM: The DDRIF supports both big endian mode where an address
of the upper byte is 0 and little endian mode where an address of the lower byte is 0. These modes
can be switched by using external pins at a power-on reset.
The data alignment shown in the following tables is used when access is made from the peripheral
modules. The data alignment in little endian mode differs from that in the physical memory map
of the DDR-SDRAM.
Table 12.2 Access and Data Alignment in Little Endian Mode (External Bus Width is 32
Rev. 1.00 Oct. 01, 2007 Page 412 of 1956
REJ09B0256-0100
Byte access at address 0
Byte access at address 1
Byte access at address 2
Byte access at address 3
Byte access at address 4
Byte access at address 5
Byte access at address 6
Byte access at address 7
Word access at address 0
Word access at address 2
Word access at address 4
Word access at address 6
Longword access at address 0 Data 31 to 24
Longword access at address 4 Data 31 to 24
Quadword access at address 0
(first time: address 0)
Quadword access at address 0
(second time: address 4)
Data Conversion
Data Alignment
Bits)
M_D31 to M_D24 M_D23 to M_D16 M_D15 to M_D8
Data 7 to 0
Data 7 to 0
Data 15 to 8
Data 15 to 8
Data 31 to 24
Data 63 to 56
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 23 to 16
Data 23 to 16
Data 23 to 16
Data 55 to 48
Data 7 to 0
Data 7 to 0
Data 15 to 8
Data 15 to 8
Data 15 to 8
Data 15 to 8
Data 15 to 8
Data 47 to 40
M_D7 to M_D0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 7 to 0
Data 39 to 32