r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1667

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

37.3.6
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the
panel.
Initial value:
Initial value:
Bit
31 to 28 
27, 26
25 to 4
3 to 0
R/W:
R/W:
Bit:
Bit:
LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
Bit Name Initial Value

SAL[25:4] All 0

R/W
31
15

R
0
0
R/W
30
14

R
0
0
R/W
All 0
All 1
All 0
29
13

R
0
0
R/W
28
12

R
0
0
R/W
27
11

R
1
0
R/W
R
R
R/W
R
R/W
26
10

R
1
0
SAL[15:4]
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Lower Panel Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data
corresponding to the lower panel
Reserved
These bits are always read as 0. The write value
should always be 0.
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 1601 of 1956
R/W
R/W
22
0
6
0
R/W
R/W
21
SAL[25:16]
Section 37 LCD Controller (LCDC)
0
5
0
R/W
R/W
20
0
4
0
R/W
19

R
0
3
0
REJ09B0256-0100
R/W
18

R
0
2
0
R/W
17

R
0
1
0
R/W
16

R
0
0
0