r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 744

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 18 Power-Down Mode

Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the

program execution state to sleep mode. Although the CPU halts immediately after executing the

SLEEP instruction, the contents of the CPU registers remain unchanged. On-chip peripheral

modules continue to operate, and the clock output on the CLKOUT pin also continues. In sleep

mode, a high level is output to the STATUS1 pin and a low level to the STATUS0 pin.

Sleep mode is canceled by an interrupt (NMI, IRQ/IRL[7:0], or on-chip peripheral module

interrupt) or a reset.

Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save SPC and

SSR to the stack before executing the SLEEP instruction.

When an NMI, IRQ/IRL[7:0], or on-chip peripheral module interrupt occurs, sleep mode is

canceled and interrupt exception handling is executed. A code indicating the interrupt source is set

Sleep mode is canceled by a power-on reset caused by the RESET pin or watchdog timer overflow

or a manual reset.

Note: If an NMI interrupt is used to cancel sleep mode while the LCD is used, the NMIFL bit in

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REJ09B0256-0100

Canceling with Interrupt

Canceling with Reset

Moreover, as the LCDC continues to output data stored in the line buffer to the LCD panel

data pin, the LCD display will be stopped if the line buffer becomes empty. Accordingly,

an NMI interrupt should be disabled and the NMIFL bit should be cleared to 0 before the

line buffer becomes empty.

the NMIFCR register is set to 1 by the interrupt. This disables the LCD to access to the

VRAM used for the display data storage (DDR_SDRAM in area 3).

Transition to Sleep Mode

Canceling Sleep Mode