r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1863

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 42 User Debugging Interface (H-UDI)
Section 42 User Debugging Interface (H-UDI)
The H-UDI is a serial interface which conforms to the JTAG (IEEE 1149.4: IEEE Standard Test
Access Port and Boundary-Scan Architecture) standard. The H-UDI is also used for emulator
connection.
42.1
Features
The H-UDI is a serial interface which conforms to the JTAG standard. The H-UDI is also used for
emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the
appropriate emulator users manual for the method of connecting the emulator.
The H-UDI has six pins: TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK. The pin
functions except ASEBRK/BRKACK and serial communications protocol conform to the JTAG
standard. This LSI has additional six pins for emulator connection: (AUDSYNC, AUDCK, and
AUDATA3 to AUDATA0). These six pins for emulator are multiplexed with on-chip modules.
And the H-UDI has one chip-mode setting pin: (MPMD).
The H-UDI has two TAP controller blocks; one is for the boundary-scan test and another is H-UDI
function except the boundary-scan test. The H-UDI initial state is for the boundary scan after
power-on or TRST asserted. It is necessary to set H-UDI switchover command to use the H-UDI
function. And the CPU cannot access the boundary scan TAP controller.
Figure 42.1 shows a block diagram of the H-UDI.
The H-UDI has the TAP (Test Access Port) controller and four registers (SDBPR, SDBSR, SDIR,
and SDINT). SDBPR supports the JTAG bypass mode, SDBSR supports the JTAG boundary scan
mode, SDIR is used for commands, and SDINT is used for H-UDI interrupts. SDIR is directly
accessed from the TDI and TDO pins.
The TAP controller, control registers and boundary scan TAP controller are initialized by driving
the TRST pin low or by applying the TCK signal for five or more clock cycles with the TMS pin
set to 1. This initialization sequence is independent of the reset pin for this LSI. Other circuits are
initialized by a normal reset.
Rev. 1.00 Oct. 01, 2007 Page 1797 of 1956
REJ09B0256-0100