r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1263

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
9
8
Bit Name
TXE
RXE
Initial
Value
0
0
R/W
R/W
R/W
Description
Transmit Enable
0: Disables data transmission from the SIOF_TXD pin
1: Enables data transmission from the SIOF_TXD pin
•
•
This bit is initialized upon a transmit reset.
Receive Enable
0: Disables data reception from SIOF_RXD
1: Enables data reception from SIOF_RXD
•
•
This bit is initialized upon receive reset.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according
to the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOF_TXD pin
begins.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOF_RXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
Rev. 1.00 Oct. 01, 2007 Page 1197 of 1956
Section 29 Serial I/O with FIFO (SIOF)
REJ09B0256-0100