r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1168

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 27 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Oct. 01, 2007 Page 1102 of 1956
REJ09B0256-0100
No
No
No
No
Figure 27.12 Sample Serial Reception Flowchart (2)
and ORER flag in SCLSR, to 0
Read receive data in SCFRDR
Clear DR, ER, BRK flags
Overrun error handling
Receive error handling
Break handling
Error handling
ORER = 1?
in SCFSR,
BRK = 1?
ER = 1?
DR = 1?
End
Yes
Yes
Yes
Yes
[1] Whether a framing error or parity error
[2] When a break signal is received,
has occurred in the receive data that
is to be read from SCFRDR can be
ascertained from the FER and PER
bits in SCFSR.
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.

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