r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1633

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

36.4.4
EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes
without being aware of this dual-FIFO configuration. However, one data write is performed for
one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at
one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64-
byte write.
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first
IN token, an IFR0/EP2 TR interrupt is requested. With this interrupt, 1 is written to the IER0/EP2
EMPTY bit, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty,
and so an EP2 FIFO empty interrupt is generated immediately.
EP2 Bulk-In Transfer (Dual FIFOs)
Data transmission to host
Clear EP2 empty status
(IFR0/EP2 EMPTY = 0)
IN token reception
in EP2 FIFO?
in EP2 FIFO?
Valid data
Space
Figure 36.11 EP2 Bulk-In Transfer Operation
Yes
No
ACK
USB function
No
Yes
NAK
empty status
EMPTY = 1)
(IFR0/EP2
Set EP2
Interrupt request
Interrupt
request
Section 36 USB Function Controller (USBF)
Rev. 1.00 Oct. 01, 2007 Page 1567 of 1956
Write one packet of data
(IER0/EP2 EMPTY = 1)
Write 1 to EP2 packet
(TRG/EP2 PKTE = 1)
to EP2 data register
Clear EP2 transfer
(IFR0/EP2 TR = 0)
Application
IFR0/EP2 EMPTY
Enable EP2 FIFO
empty interrupt
request flag
enable bit
(EPDR2)
interrupt
REJ09B0256-0100