r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 786
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
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Section 20 16-Bit Timer Pulse Unit (TPU)
Note:
Rev. 1.00 Oct. 01, 2007 Page 720 of 1956
REJ09B0256-0100
Bit
3
2 to 0
*
Bit Name
MD[2:0]
Operation when setting (BFWT, BFB, BFA) = (1, 1, 0) is the same as when setting
(BFWT, BFB, BFA) = (1, 0, 1). However, when the BFB bit is set to 1 (TGRB and TGRD
used together for buffer operation), the setting of (BFWT, BFB, BFA) = (1, 1, 1) should
be made. In this case, the value set in TGRA should also be set in TGRC because
TGRA and TGRC are also used together for buffer operation.
Initial
Value
0
000
R/W
R
R/W
Description
Reserved
This bit is always read as 0 and cannot be modified.
Modes
These bits are used to set the timer operating mode.
000: Normal operation
001: Reserved (setting prohibited)
010: PWM mode
011: Reserved (setting prohibited)
100: Phase counting mode 1
101: Phase counting mode 2
110: Phase counting mode 3
111: Phase counting mode 4
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