r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 482

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 12 DDR-SDRAM Interface (DDRIF)

Table 12.5 Register State in Each Operating Mode

Notes: 1. The initial value of bit 8 (ENDIAN bit) depends on the setting of external pins (MD5).

All bits are active-high signals and are initialized by a reset unless otherwise specified.

All access is made in longwords using the SuperHyway bus.

Rev. 1.00 Oct. 01, 2007 Page 416 of 1956

REJ09B0256-0100

Memory interface mode

DDR-SDRAM control register

DDR-SDRAM timing register

DDR-SDRAM row attribute

DDR-SDRAM mode register

DDR-SDRAM back-up register DBK

The initial value of bit 0 (SDBUP bit) depends on the setting of external pin

Abbreviation

Only writing Only writing Only