r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 439

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
11.5.4
Burst ROM Interface
Setting the TYPE bit in CSnBCR(n=0 to 2 and 4 to 6) to 010 allows a burst ROM to be connected
to areas 0 to 2 and 4 to 6. The burst ROM interface provides high-speed access to ROM that has a
burst access function. The burst access timing of burst ROM is shown in figure 11.11. The wait
cycle is set to 0 cycle. Although the access is similar to that of the SRAM interface, only the
address is changed when the first cycle ends and then the next access is started. When 8-bit ROM
is used, the number of consecutive accesses can be set as 4, 8, 16, or 32 through bits BST[2:0] in
CSnBCR(n=0 to 2 and 4 to 6). Similarly, when 16-bit ROM is used, 4, 8 or 16 accesses can be set;
when 32-bit ROM is used, 4 or 8 accesses can be set.
The RDY signal is always sampled when one or more wait cycles are set. Even when no wait is
specified in the burst ROM settings, two access cycles are inserted in the second and subsequent
accesses as shown in figure 11.12.
A writing operation for the burst ROM interface is performed in the same way as for the SRAM
interface.
In a 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus
width. The first access is performed on the data for which there was an access request, and the
remaining accesses are performed in wrap around method according to the set bus width. The bus
is not released during this transfer.
Figure 11.13 shows the timing chart when the burst ROM is used and setup/hold is specified by
CSnWCR.
Rev. 1.00 Oct. 01, 2007 Page 373 of 1956
REJ09B0256-0100