r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1032

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)

When a reception error occurs, the FR and RABT bits in EESR are set to 1 and an interrupt is

issued to the CPU after a write-back operation for the receive descriptor related to the reception

error frame.

If a reception error occurs when the length of the frame received from the GMII/MII/RMII is less

than 32 bytes, DMA transfer to the receive buffer for the frame is not performed. At this time, the

receive frame is discarded in the E-DMAC (flush function). However, if padding is inserted in the

receive frame by RPADIR, the flush function is performed when the frame length including the

padding bytes is less than 32 bytes.

(b) Receive FIFO Overflow

In any of the following cases, the E-MAC cannot receive frames from the GMII/MII/RMII

because it has no space to store receive frames, and all the receive frames that have been

transferred to the E-MAC will be discarded in the E-MAC (receive FIFO overflow).

• Receive FIFO is full of data waiting for DMA transfer (the receive FIFO has no space).

• The number of receive frames waiting for DMA transfer is 24 in total (the receive frame

If an overflow occurs due to the former case, the RFE bit in EESR is set to 1 and an interrupt is

generated to the CPU. If an overflow occurs due to the latter case, the RFCOF bit in EESR is set

to 1 and an interrupt is generated to the CPU. Each time a receive frame is discarded due to an

overflow, RMFCR is incremented. However, RMFCR is not incremented for a receive frame that

is cut off due to insufficient receive FIFO space. If a receive frame is cut off due to insufficient

receive FIFO space (the frame is partially stored in the receive FIFO), the E-DMAC performs the

following operation:

• Performs DMA transfers for the cut-off frame stored in the receive FIFO to the receive buffer.

• After the DMA transfer, performs a write-back operation on the receive descriptor.

• After the write-back operation, sets the ROC bit in EESR to 1 and generates an interrupt to the

When the receive FIFO is full of data waiting for DMA transfer, frame reception from the

GMII/MII/RMII can be resumed if DMA transfer is performed from the receive FIFO to the

receive buffer and 32 bytes or more of empty space is generated in the receive FIFO. When the

number of receive frames waiting for DMA transfer is 24 in total, frame reception from the

GMII/MII/RMII can be resumed if one or more frame has been DMA transferred from the receive

Rev. 1.00 Oct. 01, 2007 Page 966 of 1956

REJ09B0256-0100

information managing area has no empty space; up to 24 frames can be managed).

Reception Error Processing

Reception Error