r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1662

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 37 LCD Controller (LCDC)
37.3.3
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of
colors used for display so as to match the display driver software specifications.
Rev. 1.00 Oct. 01, 2007 Page 1596 of 1956
REJ09B0256-0100
Initial value:
Bit
15 to 9 
8
7
R/W:
Bit:
Bit Name
PABD

LCDC Data Format Register (LDDFR)
15

R
0
14

R
0
Initial Value
All 0
0
0
13

R
0
12

R
0
11

R
0
R/W
R
R/W
R
10

R
0

R
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Byte Data Pixel Alignment
Sets the pixel data alignment type in one byte of
data. The contents of aligned data per pixel are the
same regardless of this bit's setting. For example,
data H'05 should be expressed as B'0101 which is
the normal style handled by a MOV instruction of the
this CPU, and should not be selected between
B'0101 and B'1010.
0: Big endian for byte data
1: Little endian for byte data
Reserved
This bit is always read as 0. The write value should
always be 0.
PABD
R/W
8
0

R
7
0
R/W
6
0
R/W
5
0
R/W
4
0
DSPCOLOR[6:0]
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0