r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 605
r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
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When all the MBARE bits in PCILSR0/1 are 0, the PCI local bus address is sent to the
SuperHyway bus without translation.
Data prefetching for memory read commands is supported. When a PCI burst read is performed, 8
bytes, or 32 bytes of data block is prefetched. (this depends on the settings of the PFE and PFCS
bits in PCICR).
(2)
Allocate a 256-byte area to the I/O address space.
Address translation from PCI local bus to SuperHyway bus
The lower 8 bits ([7:0]) are sent to the SuperHyway bus without translation.
When bits 31 to 8 of a PCI local bus address match bits 31 to 8 in a PCI I/O base address register
(PCIIBAR), the upper 24 bits of a PCI local bus address are replaced with H'FE04 01.
PCIMBAR0/1
PCI address
PCILSR0/1
Accessing PCIC I/O Space
31
31
31
0 0 0 0 0 1
Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation
compare
2928
29 28
2928
MBA (upper)
20 19
2019
2019
1 0 0
(Local Address Space 0/1)
0
1
0/1
0
0
0
SH address
PCILAR0/1
Rev. 1.00 Oct. 01, 2007 Page 539 of 1956
31
31
2928
2928
Section 13 PCI Controller (PCIC)
LAR
2019
2019
REJ09B0256-0100
0
0
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