r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 610

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)
(7)
The PCIC supports cache snoop function.
When the PCIC functions as a target device, cache coherency is guaranteed for accesses from a
master device connected to a PCI bus in both the host bus bridge mode and normal mode.
When accessing this LSI cacheable area, set the cache snoop registers: the PCI cache snoop
control registers (PCICSCR0 and PCICSCR1) and PCI cache snoop address register (PCICSAR0
and PCICSAR1).
Usage Notes
• Up to 2 conditions can be set as snoop address. Address comparison is logical OR of setting 2
• When using this function, execute memory read or write after flush/purge request issued to the
• When using this function, do not use the prefetch function.
• Do not use this function when the CPU is sleep state. If cache hit occurs in sleep state, it
• Do not use ether of the following functions and the cache shoop function simultaneously.
Rev. 1.00 Oct. 01, 2007 Page 544 of 1956
REJ09B0256-0100
conditions.
CPU cache in the access of cache hit. It reduces PCI bus transfer speed and CPU performance.
(Do not set PFE bit in the PCICR to 1.)
becomes an error access on the SuperHyway bus, and memory read or memory write does not
execute. Specify the SNPMD bit in the PCICSCR to 00 before the CPU enters sleep mode. To
keep the coherency before and after the CPU sleep, cache purge should be executed before
sleep instruction executed.
 Debug function using an emulator (Disable this function when using an emulator).
 L memory or memory mapped cache access from the DMAC.
Cache Coherency