r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 70

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 1 Overview
Rev. 1.00 Oct. 01, 2007 Page 4 of 1956
REJ09B0256-0100
Item
Memory
management
unit (MMU)
Cache memory
LRAM
User break
controller (UBC)
Features
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4 Gbytes of physical address space, 256 address spaces (identified by
an 8-bit ASID (address space identifier))
Supports single virtual memory mode and multiple virtual memory mode
Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, or 1 Mbytes
4-entry full associative TLB for instructions
64-entry full associative TLB for instructions and operands
Supports software-controlled replacement and random-counter
replacement algorithms
Contents of TLB are directly accessible through address mapping
Instruction cache (IC)
 32-Kbyte 4-way set associative
 32-byte block length
Operand cache (OC)
 32-Kbyte 4-way set associative
 32-byte block length
 Selectable write method (copy-back or write-through)
Storage queue (32 bytes × 2 entries)
High-speed memory (16 Kbytes)
Two independent read/write ports
 8-/16-/32-/64-bit access from the CPU/FPU
 8-/16-/32-/64-bit access from the DMAC
Supports memory protective mechanism
Supports debugging by means of user break interrupts
Two break channels
Address, data value, access type, and data size are available as break
condition settings
Supports sequential break functions