r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 659

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer

destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer

request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive

data register. These conditions also apply to the SCIF1, SCIF2, HAC USBF, SSI0 to SSI3,

MMCIF, SIM, SIOF0 to SIOF2, STIF0, and STIF1.

Table 14.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0]

DMA Transfer

DMA Transfer

Request Signal

Compare-match transfer

Compare-match transfer

Compare-match transfer

Compare-match transfer

Compare-match transfer

TXI (transmit FIFO data

empty interrupt)

RXI (receive FIFO data

full interrupt)

TXI (transmit FIFO data

empty interrupt)

RXI (receive FIFO data

full interrupt)

TXI (transmit FIFO data

empty interrupt)

RXI (receive FIFO data full

Transmit data empty request Any

Receive data is not read

Transmit data empty request Any

Receive data full request

Transmit mode : DMRQ = 1

(Transmit data empty

Receive mode : DMRQ = 1

(Receive data is not read)

Section 14 Direct Memory Access Controller (DMAC)

Rev. 1.00 Oct. 01, 2007 Page 593 of 1956

REJ09B0256-0100