r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 219

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

6.2.7
When the specific resource is changed, IRMCR controls whether the instruction fetch is
performed again for the next instruction. The specific resource means the part of control registers,
TLB, and cache.
In the initial state, the instruction fetch is performed again for the next instruction after changing
the resource. However, the CPU processing performance will be lowered because the instruction
fetch is performed again for the next instruction every time the resource is changed. Therefore, it
is recommended that each bit in IRMCR is set to 1 and the specific instruction should be executed
after all necessary resources have been changed prior to execution of the program which uses
changed resources.
For details on the specific sequence, see descriptions in each resource.
Bit
7 to 0
Instruction Re-Fetch Inhibit Control Register (IRMCR)
Bit Name
UB
Initial
Value
All 0
R/W
R/W
Description
Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or in
the cache write-through mode, these bits specify
whether the next bus access from the CPU waits for the
end of writing for each area.
0: The CPU does not wait for the end of writing bus
1: The CPU waits for the end of writing bus access and
UB[7]: Corresponding to the control register area
UB[6]: Corresponding to area 6
UB[5]: Corresponding to area 5
UB[4]: Corresponding to area 4
UB[3]: Corresponding to area 3
UB[2]: Corresponding to area 2
UB[1]: Corresponding to area 1
UB[0]: Corresponding to area 0
access and starts the next bus access
starts the next bus access
Section 6 Memory Management Unit (MMU)
Rev. 1.00 Oct. 01, 2007 Page 153 of 1956
REJ09B0256-0100