r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 651
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 651 of 2026
- Download datasheet (12Mb)
Bit
9, 8
7 to 3
2
Bit Name
PR[1:0]
—
AE
Initial
Value
00
0
All 0
R/W
R/W
R
R/(W)* Address Error Flag
Descriptions
Priority Mode 1, 0
Select the priority level between channels when there
are transfer requests for multiple channels
simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates that an address error occurred during DMA
transfer.
This bit is set under following conditions:
•
•
•
bit in CHCR and the DME bit in DMAOR are set to 1.
0: No DMAC address error
[Clearing condition]
Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
If this bit is set, DMA transfer is disabled even if the DE
The value set in SAR or DAR does not match to the
transfer size boundary.
The transfer source or transfer destination is invalid
space.
The transfer source or transfer destination is in
module stop mode
Section 14 Direct Memory Access Controller (DMAC)
Rev. 1.00 Oct. 01, 2007 Page 585 of 1956
REJ09B0256-0100
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