r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 626

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)

By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the

PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function

can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the

stipulated logic level in one clock.

When the PCIC operates as the host bus bridge mode, it is recommended to use this function for

the issuance of configuration transfers.

Figure 13.25 is an example of burst memory write cycle with stepping. Figure 13.26 is an example

of target burst read cycle with stepping.

Rev. 1.00 Oct. 01, 2007 Page 560 of 1956

REJ09B0256-0100

Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping)

Address/Data Stepping Timing

PCI space address

Address parity

nth data parity

nth data byte enable