r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1098

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 26 I
Rev. 1.00 Oct. 01, 2007 Page 1032 of 1956
REJ09B0256-0100
Bit
4
3
2
1
2
C Bus Interface (IIC)
Bit Name
SSR
SDE
SDT
SDR
Initial Value
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Slave Stop Received
A stop condition has been output on the bus.
This status bit becomes active after the rising
edge of SDA during the stop bit.
Slave Data Empty
Indicates that data to be transmitted has been
loaded into the shift register. At the start of
byte data transmission, the contents of the
ICTXD register are loaded into a shift register
ready for outputting data on the bus. This
status bit indicates that data has been loaded
and the ICTXD register is again ready for
further data. This status bit becomes active on
the falling edge of SCL before the first data bit.
During the single-buffer mode, this bit must be
reset every time new data has been written to
the ICTXD register. This is because the slave
holds SCL low to stop the bus while this bit is
set to 1 even if a slave transmission cycle is
started.
Slave Data Transmitted
A byte of data has been transmitted to the bus.
This bit becomes active after the falling edge
of SCL during the last data bit.
Slave Data Received
A byte of data has been received from the bus
and is ready for read in the receive data
register. This bit becomes active after the
falling edge of SCL during the last data bit.
During the single-buffer mode, this bit must be
reset after data has been read from the ICRXD
register.
When SDBS is set to 1, SCL will be held low
from the timing when the receive data register
acquires the data packet until the SDR flag is
cleared.