r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 373

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.5.2
When handling multiple interrupts, an interrupt handling routine should include the following
procedures:
1. To identify the interrupt source, branch to a specific interrupt handling routine for the interrupt
2. Clear the interrupt source in each specific interrupt handling routine.
3. Save SSR and SPC to the stack.
4. Clear the BL bit in SR. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level
5. Handle the interrupt as required.
6. Set the BL bit in SR to 1.
7. Restore SSR and SPC from memory.
8. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted if multiple interrupts occur after step 4. This reduces the interrupt
response time for urgent processing.
9.5.3
Setting the MAI bit in ICR0 to 1 masks interrupts while the NMI signal is low regardless of the
BL and IMASK bit settings in SR.
• Normal operation or sleep mode
All interrupts are masked while the NMI signal is low. Note that only NMI interrupts due to NMI
signal input occur.
source by using the INTEVT code as an offset.
(IMASK) in SR is automatically modified to the level of the accepted interrupt. When the
INTMU bit in CPUOPM is cleared to 0, set the IMASK bit in SR by software to the accepted
interrupt level.
Multiple Interrupts
Interrupt Masking by MAI Bit
Rev. 1.00 Oct. 01, 2007 Page 307 of 1956
Section 9 Interrupt Controller (INTC)
REJ09B0256-0100