r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1274

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 29 Serial I/O with FIFO (SIOF)
Rev. 1.00 Oct. 01, 2007 Page 1208 of 1956
REJ09B0256-0100
Bit
1
0
Bit Name
RFUDF
RFOVF
Initial
Value
0
0
R/W
R/W
R/W
Receive FIFO Overflow
Description
Receive FIFO Underflow
0: No receive FIFO underflow
1: Receive FIFO underflow
A receive FIFO underflow means that reading of
SIRDR has occurred when the receive FIFO is empty.
When a receive FIFO underflow occurs, the value of
data read from SIRDR is not guaranteed.
•
•
•
0: No receive FIFO overflow
1: Receive FIFO overflow
A receive FIFO overflow means that writing has
occurred when the receive FIFO is full.
When a receive FIFO overflow occurs, the SIOF
indicates overflow, and receive data is lost.
•
•
•
This bit is valid when the RXE bit in SICTR is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
This bit is valid when the RXE bit in SICTR is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.