r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 414

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 348 of 1956
REJ09B0256-0100
Bit
19
18 to 16 RDH
15
14 to 12 WTS
Bit Name


Initial
Value
0
111
0
111
R/W
R
R/W
R
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
RD Hold Cycle (RD Negate–CSn Negate Delay Cycle)
Specify the number of cycles to be inserted to ensure
the RD hold time to the T2. However, setting to over 1
cycle for insertion, one cycle incremented for the setting
value when address hold cycle is set to over 1 cycle.
(Available only when the SRAM interface, byte control
an SRAM interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
WEn Setup Cycle (CSn Assert–WEn Assert Delay
Cycle)
Specify the number of cycles to be inserted to ensure
the WE setup time to the T2. (Available only when the
SRAM interface, byte control an SRAM interface, or
burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted