r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 422

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
11.5
11.5.1
This LSI supports both big-endian mode, in which the upper byte (MSByte) in a string of byte
data is at address 0, and little-endian mode, in which the lower byte (LSByte) in a string of byte
data is at address 0. The mode is specified by the external pin (MD5 pin) at a power-on reset
through the RESET pin. At a power-on reset by PRESET, big-endian mode is specified when the
MD5 pin is low, and little-endian mode is specified when the MD5 pin is high.
A data bus width of 8, 16, or 32 bits can be selected for the normal memory interface, and one of 8
or 16 bits can be selected for the PCMCIA interface. Data alignment is carried out according to
the data bus width and endian mode of each device. Accordingly, when the data bus width is
smaller than the access size, multiple bus cycles are automatically generated to reach the access
size. In this case, access is performed by incrementing the addresses corresponding to the bus
width. For example, when a longword access is performed at the area with an 8-bit width in the
SRAM interface, each address is incremented one by one, and then access is performed four times.
In the 32-byte transfer, a total of 32-byte data is continuously transferred according to the set bus
width. The first access is performed on the data for which there was an access request, and the
remaining accesses are performed in wrap around method according to the set bus width. The bus
is not released during these transfers. In this LSI, data alignment and data length conversion
between different interfaces is performed automatically.
The relationship between the endian mode, device data length, and access unit are shown in tables
11.9 to 11.14.
Data Configuration
Rev. 1.00 Oct. 01, 2007 Page 356 of 1956
REJ09B0256-0100
Byte
Word
Longword
Quadword
Operation
Endian/Access Size and Data Alignment
MSB
MSB
MSB
MSB
63 to 56
Data
Data 31 to 24
Data 15 to 8
Data 7 to 0
55 to 48
Data
LSB
47 to 40
Data
Data 23 to 16
Data 7 to 0
39 to 32
Data
LSB
31 to 24
Data
Data 15 to 8
23 to 16
Data
15 to 8
Data
Data 7 to 0
7 to 0
Data
LSB
LSB