r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1643

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

36.8
36.8.1
This section describes stall operations in this module. There are two cases in which the USB
function controller stall function is used:
• When the application forcibly stalls an endpoint for some reason
• When a stall is performed automatically within the USB function controller due to a USB
The USB function controller has internal status bits that hold the status (stall or non-stall) of each
endpoint. When a transaction is sent from the host, the module references these internal status bits
and determines whether to return a stall to the host. These bits cannot be cleared by the
application; they must be cleared with a Clear Feature command from the host.
However, the internal status bit to EP0 is automatically cleared only when the setup command is
received.
36.8.2
The application uses the EPSTL register to issue a stall request for the USB function controller.
When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (1-
1 in figure 36.17). The internal status bits are not changed at this time. When a transaction is sent
from the host for the endpoint for which the EPSTL bit was set, the USB function controller
references the internal status bit, and if this is not set, references the corresponding bit in EPSTL
(1-2 in figure 36.17). If the corresponding bit in USBEPSTL is set, the USB function controller
sets the internal status bit and returns a stall handshake to the host (1-3 in figure 36.17). In this
time, if the CTLR/ASCE bit is set to 1, the corresponding bit in EPSTL is automatically cleared to
0 and a stall handshake is returned to the host (1-4 in figure 36.17). If the corresponding bit in
EPSTL is not set, the internal status bit is not changed and the transaction is accepted.
Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the
host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature
command (3-1 in figure 36.17), the USB function controller continues to return a stall handshake
while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed
for the corresponding endpoint (1-2 in figure 36.17). To clear a stall, therefore, it is necessary for
the corresponding bit in EPSTL to be cleared automatically when a stall is returned from the USB
controller while the CTLR/ASCE bit is set to 1, or to be cleared by the application, and also for
the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure
36.17).
specification violation
Stall Operations
Overview
Forcible Stall by Application
Section 36 USB Function Controller (USBF)
Rev. 1.00 Oct. 01, 2007 Page 1577 of 1956
REJ09B0256-0100