r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1314

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 30 SIM Card Module (SIM)
30.3.3
SCSCR is an 8-bit readable/writable register that selects transmit or receive operation, the serial
clock output, and whether to enable or disable interrupt requests for the smart card interface.
Rev. 1.00 Oct. 01, 2007 Page 1248 of 1956
REJ09B0256-0100
Bit
7
6
Bit Name
TIE
RIE
Serial Control Register (SCSCR)
Initial
Value
0
0
Initial value:
R/W:
Bit:
R/W
R/W
R/W
R/W
TIE
7
0
R/W
RIE
Description
Transmit Interrupt Enable
When serial transmit data is transferred from the transmit
data register (SCTDR) to the transmit shift register
(SCTSR), and the TDRE flag in the serial status register
(SCSSR) is set to 1, transmit data empty interrupt (TXI)
requests are enabled/disabled.
0: Disables transmit data empty interrupt (TXI) requests*
1: Enables transmit data empty interrupt (TXI) requests
Note: * A TXI can be canceled either by clearing the
Receive Interrupt Enable
When serial receive data is transferred from the receive
shift register (SCRSR) to the receive data register
(SCRDR), and the RDRF flag in SCSSR is set to 1, receive
data full interrupt (RXI) requests, and transmit/receive error
interrupt (ERI) requests due to parity errors, overrun errors,
and error signal status are enabled/disabled.
0: Disables receive data full interrupt (RXI) requests and
1: Enables receive data full interrupt (RXI) requests and
Notes:
6
0
transmit/receive error interrupt (ERI) requests*
transmit/receive error interrupt (ERI) requests*
R/W
TE
5
0
TDRE flag, or by clearing the TIE bit to 0.
1. RXI and ERI interrupt requests can be
2. Wait error interrupt (ERI) requests are enabled
R/W
RE
4
0
canceled either by clearing the RDRF, PER,
ORER or ERS flag, or by clearing the RIE bit to
0.
or disabled by using the WAIT_IE bit in
SCSCR.
WAIT_
R/W
IE
3
0
TEIE
R/W
2
0
R/W
1
0
CKE[1:0]
R/W
0
0
1
2
*
2